ics for communications two/four channel codec filter for terminal applications sicofi ? -2/4-te psb 2132 version 1.4 psb 2134 version 1.4 delta sheet 1998-04-01 ds 1
psb 2132 psb 2134 revision history: current version: 1998-04-01 previous version: none page (in previous version) page (in current version) subjects (major changes since last revision) abstract of changes with the redesign of the sicofi-2/4-te all known erratas of version v1.2 were corrected according to the data sheet 09.97. effect of changes see detailed describtion as follows. edition 1998-04-01 published by siemens ag, hl sp, balanstra?e 73, 81541 mnchen ? siemens ag 1998. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for application s, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens compa nies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreeme nt we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for an y costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sust ain hu- man life. if they fail, it is reasonable to assume that the health of the user may be endangered. sicofi ? , sicofi ? -2, sicofi ? -4 and sicofi ? -4 m c are registered trademarks of siemens ag. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide: see our webpage at http://www.siemens.de/semiconductor/address/address.htm.
two/four channel codec filter for terminal applications sicofi ? -2/4-te psb 2132 psb 2134 semiconductor group 3 1998-04-01 delta sheet for the version 1.4 1 interrupt handling if all the inputs assigned to channel-pair-1,2 (or 3,4) have been stable for two samples (i.e. for at least the debounce time), an interrupt on int12 (or int34) is generated. the status information will be read into the xr-registers with the rising edge of int12 (or int34). the status information of the assigned channel-pair-1,2 (or 3,4) will be updated after the next interrupt int12 (or int34) has occurred. the interrupt int12 (or int34) of assigned channel-pair-1,2 (or 3,4) is cleared, if the registers xr0-xr3 are read via a xop command. ? the signaling inputs (six_x and sbx_x, if programmed as inputs) are sampled after the debounce time (refer to xr4) ? int12 is assigned to and affected by the signaling inputs of channel-pair-1,2 ? int34 is assigned to and affected by the signaling inputs of channel-pair-3,4
psb 2132 psb 2134 interrupt handling semiconductor group 4 1998-04-01 figure 1 example for channel-pair-1,2 if one or more of the signaling input pins for channel-pair-1,2 (input pins and bi-directional pins programmed as inputs) change, and all these signaling inputs for channel-pair-1,2 are stable for at least the debounce time specified in register xr4 int12 will go from 0 to 1. the assigned interrupt int12 is cleared if the appropriate registers (xr0, xr1, xr2 and xr3, read with command xop := 3b h ) are read via the serial m c-interface. note: pin int34 provides the same functionality for channel-pair-3,4. changes at the signaling inputs assigned to channel-pair-3,4 do not affect int12 and vice versa! its10545 control-unit c m interface int12-unit xr input-bits, assigned to channel-pair 1, 2 int12 si1_0 si1_1 sb1_0 sb1_1 sb1_2 si2_0 si2_1 sb2_0 sb2_1 sb2_2 sbx_x, programmed as inputs ! inputs, channel 1 channel 2 inputs, int34-unit xr input-bits, assigned to channel-pair 3, 4 sbx_x, programmed as inputs ! sb3_2 sb4_2 si4_1 si4_0 sb4_0 sb4_1 sb3_1 sb3_0 si3_1 si3_0 int34 inputs, channel 4 inputs, channel 3
psb 2132 psb 2134 interrupt handling semiconductor group 5 1998-04-01 the following example shows the interrupt functionality of channel-pair-1,2, sbx_x are programmed as outputs: figure 2 example, status information in xr-registers for both channel-pairs 1,2 and 3,4 the status information of the appropriate channel-pair-1,2 (or 3,4) will be read into the xr-registers with the rising edge of int12 (or int34) and remains valid until the next rising edge of int12 (or int34) updates the status information. the assigned interrupt int12 is cleared if the appropriate registers (xr0, xr1, xr2 and xr3, read with command xop := 3b h ) are read via the serial m c-interface. itd10546 after xop read-command, int12 is cleared ! (read xr3, xr2, xr1, xr0 within the interrupt-handler) si1_0 change change no change change change stable change change change change stable no change samples si1_1 si2_0 si2_1 int12 debounce time, adjusted in xr4
psb 2132 psb 2134 interrupt handling semiconductor group 6 1998-04-01 figure 3 itd10547 after xop read-command, int12 is cleared ! (read xr3, xr2, xr1, xr0 within the interrupt-handler) si1_0 change change no change change change stable change change change change stable no change samples si1_1 si2_0 si2_1 int12 debounce time, adjusted in xr4 (read xr3, xr2, xr1, xr0 within the interrupt-handler) after xop read-command, int12 is cleared ! int34 si3_1 si3_1 si2_0 si2_1 si1_1 si1_0 xr-register, status information of channel-pair 1, 2 (or 3,4) is updated with the positive edge of int12 (or 3, 4)
psb 2132 psb 2134 xr4 extended register 4 semiconductor group 7 1998-04-01 2 xr4 extended register 4 register xr4 provides two optional functions: debouncing of signaling input changes, and the configuration of the programmable output pin rgen. signaling debounce interval n to restrict the rate of changes on signaling input pins, deglitching of the status information from the slic may be applied. an interrupt on pin int12 (or int34) will be generated, after all inputs of the assigned channel-pair-1,2 (or 3,4) have been stable for n milliseconds. new status information of the affected channel-pair-1,2 (or 3,4) will be read into registers xr0, xr1 and xr3 with the rising edge of the assigned interrupt int12 (or int34). the status information stays valid until the next interrupt int12 (or int34) occurs to update the xr-registers. n is programmable in the range of 2 to 26 ms in steps of 2 ms. if n is programmed to 1111, the debounce time is adjusted to 0.5 ms. the bit combination n = 1110 is reserved for future use. with n = 0 the debouncing and the interrupt generation is disabled, the current signaling status can be read via the m c-interface (xop-read command). bit76543210 nt table 1 field n debounce interval time 0 0 0 0 debounce and interrupt generation is disabled 0 0 0 1 debounce period 2 ms 0 0 1 0 debounce period 4 ms ..... ..... 1 1 0 1 debounce period 26 ms 1110reserved 1 1 1 1 debounce period 0.5 ms
psb 2132 psb 2134 signaling interface semiconductor group 8 1998-04-01 3 signaling interface due to the correction of the interrupt handling, it is necessary to apply a valid clock signal to the dcl pin. polling the signaling interface is not possible without the dcl clock running. 4 xr5 extended register 5 a crash occurs, if 2 or more channels are programmed to transmit (talk) in the same timeslot on the same highway. in this case a crash-bit will be set and transmission will be disabled for all affected channels. after correct timeslot programming (cr5 of the effected channels), the crash-bit will be cleared after xr5 was read. the version-bitfield identifies the current chip version and has been changed to 01 in version v1.4. table 2 configuration of rgen field t frequency applied to pin rgen 0 0 0 0 rgen is set to 1 permanently 0001t is 2 ms 0010t is 4 ms ..... ..... 1101t is 26 ms 1110t is 28 ms 1 1 1 1 rgen is set to 0 permanently bit76543210 0 0 cr_du cr_dd chclk version
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